The present invention concerns the field of integrated circuit manufacturing and pertains particularly to generation of masks with patterned fill.
When processing integrated circuits, masks are utilized to pattern and etch layers of material deposited on a wafer. These layers are composed of, for example, polysilicon, metal or oxide.
The trend in integrated circuit manufacturing is to increase the amount of circuitry within each individual integrated circuit. Along with this trend there is an increase in the number of layers used and a decrease in the dimensions of the patterned material.
The planarity of topology underlying a deposited layer of material can have a significant impact on the ability to pattern and etch the deposited layer. As the numbers of layers increase and the dimensions of the patterns decrease, the planarity of topology underlying some layers, particularly the interconnect layers such as polysilicon layers and metal layers, can be significantly affected. Each additional interconnect layer increases the variation in step heights for the interconnect layers above. However, when patterning and etching these top interconnect layers, the depth of focus for high resolution photolithograpic step and exposure systems used to pattern these top layers limits the amount of planar variation in the underlying topology that can be tolerated.
Various methods have been used to increase planarization in topology. For example, a spin-on glass (SOG)/etchback process can be used. In the SOG/etchback process, after patterning and etching certain layers, spin on glass flows over the wafer filling narrow gaps. SOG/etchback is a cost effective method to improve local planarization of the layer. See, for example, S. Wolf, Silicon Processing for the VLSI Era, Vol. 2--Process Integration, Lattice Press 1990, pp. 229-236. While effective for filling narrow gaps, this SOG/etchback process is ineffective in reducing height differences between dense regions having a lot of circuitry and open regions including little or no circuitry.
Another method used to increase planarity is a chemical mechanical polishing process used after deposition of dielectric layers. See for example, D. Webb, S. Sivaram, D. Stark, H. Bath, J. Draina, R. Leggett, and R. Tolles, Complete Intermetal Planarization Using ECR Oxide and Chemical Mechanical Polish, 1992 ISMIC, pp. 141-148. However, this method has not proved cost-effective.